Editor’s Note: This paper was given at DesignCon 2021 and selected as a Best Paper Award finalist. Below is a summary/introduction with a link to the PDF of the complete paper.
The high-speed electronics industry is in the process of migrating serial links from 56 Gb/s to 112 Gb/s. Typically, these links use PAM-4 protocol and have Nyquist frequencies of 14 and 28 GHz, respectively. Recent studies indicate that the industry is nearing the precipice where plated through-hole (PTH) via technology has reached a limit in supporting serial links with 28 GHz Nyquist frequency requirements. Additionally, printed circuit board (PCB) fabricators appear unwilling to broadly support advanced technologies such as stacked micro/laser vias for high-layer count boards. Therefore, the high-speed electronics industry must develop ways to adapt evolutionary PCB technologies that introduce increasingly deeper micro/laser vias and yet still have some layers accessible with 28 GHz PTH vias.
As described in a previous paper based on a specially designed test board, it is very difficult to design a PTH via in PCB technology with low reflected voltage (S11) up to 28 GHz. Nevertheless, several stripline layers that employed well-designed PTH vias were shown to be capable of supporting 112 Gb/s PAM-4 links.
More recently, the same test board artwork was fabricated by a different manufacturer. When tested under similar conditions as the original board, the PTH vias exhibited significantly reduced performance. Specifically, the performance of the second board did not meet 28 GHz reflected voltage requirements. While the results from the first board that showed that PCBs using PTH via technology could support 28 GHz Nyquist frequencies were somewhat surprising, it was likewise unexpected to see such a significant impact on the performance of the second board due to a change in PCB fabricator.
This paper describes the investigation that ensued as well as proposes a strategy for adding verifiable manufacturing specifications targeted directly at ensuring PCB via high-frequency performance. Signal integrity engineers have long enforced characteristic impedance specifications for high-speed PCB transmission line routing. More recently, additional requirements have emerged to reduce trace losses, such as specifying low-loss copper roughness treatments. However, to further enable next generation high-speed links, it has become necessary to formulate new specifications targeting via technology electrical performance.
First, the via performance is contrasted between two PCB fabricators along with an analysis of the physical construction differences that impacted signal integrity measurement results. Next, a suggested set of manufacturer specifications for via designs to meet high-bandwidth electrical requirements is offered. A requirement placed on these proposed specifications is that they must be easily verifiable by the manufacturer. Typically, a PCB manufacturer does not have the capability to validate high-frequency via performance through electrical measurement. These specifications include physically-verifiable aspects such as finished pad and antipad sizes, layer-to-layer registration, and “effective” via barrel diameter requirements. Fabrication specifications for laser-blind vias are also included because this technology increases the number of 112G-capable routing layers for a board that is otherwise limited to PTH vias.
The proposed specifications extend the “life” of conventional PCB technology. This may offer time for PCB manufacturers to develop more advanced via technologies for links faster than 112G PAM-4.
Download the entire paper here.