Articles Tagged with ''SerDes''

In this paper, John Baprawski gives an overview of modeling SerDes systems in a channel simulator, introduces the zero-cost tools available at SerDesDesign.com, and gives an example of simulating a SerDes system with Tx and Rx IBIS-AMI models – all to bring the SI engineer a low cost path for modeling and simulating SerDes systems.

This paper presents two modeling methodologies for ADC-based SerDes that mitigate IBIS-AMI architectural misalignments, and a corresponding model correlation methodology.

With the growth of 5G data traffic and AI computing, data centers need faster connectivity to meet the increasing bandwidth. High speed I/O speed beyond 112 Gb/s per lane is required. If we follow the SerDes technology revolution by doubling the data rate per lane in every 2-3 years, the next generation I/O data rate will be 224 Gb/s. In this article, Cathy Liu explores options, technical challenges, and potential solutions to achieve 224 Gb/s per lane.

Those interested in automating signal integrity analysis using machine learning should take a look at this work, which includes an example of a 112 Gb SerDes system analysis.

Uniform transmission lines are best suited for high-speed data transmission because of their broadband impedance characteristics. In some applications, a minor deviation from uniformity can help in optimizing other desired signal integrity metrics. This paper addresses some of the challenges involved with this approach.

In the future, the complexity of circuit implementation will increase dramatically and modeling of high-speed SerDes systems will continue to be a huge challenge. Modeling equalization circuit characteristics has become extremely important to ensure the success of the final platform implementation and provide a strong signal integrity design guide. This paper reviews the common challenges of converting an existing detailed architectural model to an IBIS-AMI model and some of the ways to address these challenges. It also includes an illustration of the workflow to model Intel’s 56G PAM4 SerDes.

Routing 112 Gbps PAM4 signals through a system poses many challenges for designers. In this piece, SI expert Scott McMorrow explains what causes signal degradation and offers a path forward.

Architectural decisions depend on the ability to adequately analyze the link. This paper presents a methodology to model and evaluate the performance of both center and edge sampling schemes.

Data converter based SerDes designs are gaining popularity due to their architecture flexibility as well as the capability to implement FFE through powerful DSP. This paper provides a theoretical analysis, realistic simulations and practical comparisons between TX side FFE and RX side FFE.