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Optimizing DDR5 memory system validation involves a strategic focus on probe and interposer solutions for in-system measurements. The selection of probe architecture, whether RC or RCRC, plays a key role in managing probe loading. To make the right choice, evaluating source impedance and signal characteristics, especially for bursted signaling, is essential. As DDR5 continues to evolve at higher speeds and reach its top speed phase, integrating non-ideal loading modeling within simulations and effectively de-embedding probe and interposer effects become critical components of a comprehensive testing plan.s

Serial links have focused the practice of signal integrity on managing loss and discontinuities. Each system struggles with one or the other, making it imperative to determine which issue is dominant in your system and respond appropriately. This article by Donald Telian will explain how to characterize your link to help guide your thinking and your solution.

In this article, Donald Telian explains why discontinuities do not sum the same way as loss. Telian outlines that a failing an RL mask might indicate that Tx or Rx are simply too close to a discontinuity, causing the discontinuity proximity effect. Read on to learn more about how to to distance SerDes from discontinuities.

This article is the first part of a trilogy that aims to introduce a new paradigm in the measurement of specific electromagnetic shielding materials, namely shielding materials made from woven conductive threads. These articles highlight the shortcomings of common methods in the evaluation of such materials and introduce new approach and methodology to measure them. This new paradigm emphasizes characterization of shielding materials based on magnetic field rather than electric field. The new method introduces a measurement setup and lumped element model intrinsic to the material and independent from the measurement method.

In the process of circuit design, electrical engineers must carefully position capacitors to decouple the power supply pins of integrated circuits (ICs). Yet, relying solely on a single capacitor for this purpose may potentially decrease the performance of the Power Delivery Network (PDN). Therefore, there exists a need for an elegant and systematic methodology in designing the PDN while utilizing a single capacitor. Within this paper, we analyze the single-capacitor scenario within the context of the PDN and introduce a systematic approach for its design. This approach not only suggests clear guidelines for when favoring a single capacitor over multiple capacitors is appropriate but also showcases that when these guidelines are exceeded, this method can be implemented recursively to achieve an optimal PDN solution.

Automotive applications present new challenges to high-speed serial technology. Asymmetric, multi-gigabit signaling between sensors, processors, and displays in the unique noise environments of both electric and internal combustion engine vehicles create new problems for signal and power integrity engineers. This paper introduces the signal impairments required for receiver testing in the emerging automotive standards like ASA, MIPI's A-PHY, Automotive Ethernet, and more. Standards specify different sources of noise in different ways, some in the form of time evolutions, others as spectra. This paper focuses on techniques for generating and calibrating each noise source while describing advanced de-embedding techniques and addressing test equipment limitations.

Where do those strange frequency domain “Kramers-Kronig” equations come from? They don’t seem to have any obvious intuitive basis. Looking at their time domain equivalents, however, resolves the mystery and gives us an intuitive understanding of their origin.

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

The roughness of copper foils has a detrimental effect on signal loss in PCBs. Therefore, reducing roughness is crucial in minimizing signal loss. Nevertheless, roughness is essential to ensure a good adherence between the prepreg and the copper foil. A compromise must be found between adherence and power integrity. This paper presents a novel approach to evaluate signal loss without assuming any specific roughness shape.    

This paper demonstrates a step-by-step correlation methodology adapted for DSP-based PCIe Gen5 and Gen6 IBIS-AMI models where one can measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.