Items Tagged with 'DesignCon2023'

This paper addresses the challenge of how to simulate the power integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation.

This paper investigates via and trace coupling effects using measurements, hybrid, and full-wave solvers by de-embedding/calibration utilizing multiple test-boards.

The roughness of copper foils has a detrimental effect on signal loss in PCBs. Therefore, reducing roughness is crucial in minimizing signal loss. Nevertheless, roughness is essential to ensure a good adherence between the prepreg and the copper foil. A compromise must be found between adherence and power integrity. This paper presents a novel approach to evaluate signal loss without assuming any specific roughness shape.    

This paper demonstrates a step-by-step correlation methodology adapted for DSP-based PCIe Gen5 and Gen6 IBIS-AMI models where one can measure and directly correlate raw errors out of the DSP on a test setup that is based on the receiver stress eye methodology of the PCIe standard.

Design of PCB-based PDNs has become a challenge due to rising power consumption, lowering supply voltages, increasing integration density and design complexity. In this paper, we propose an algorithmic procedure using supervised machine learning techniques to provide expert guidance on the PDN design and optimize power supply decoupling capacitors. The proposed method replaces the computationally expensive numerical simulations with faster ANNs.

This paper proposes a model that can serve as a tool for evaluating FEC choices in 200+ Gb/s applications. It allows the comparison of the effect of different inner/outer codes and inner-FEC interleaving schemes on post-FEC BER. It can also be used as a tool for system-level transceiver design, allowing designers to see the impact of design choices on the post-FEC BER efficiently.